The present invention generally relates to analog-to-digital (A/D) converters and, more particularly, to a pipelined monolithic A/D architecture which overcomes the performance limitations of previous pipelined architectures through the use of a new parallel-autozero analog signal processing scheme requiring a smaller gain-bandwidth product and being able to achieve a higher resolution at a higher speed with less accurate matching of components. The architecture of the invention can be applied to the realization of high-resolution (greater than twelve bits), high-speed (greater than twenty megaHertz (MHz)), small area (less than 10,000 square mils), and low-power (less than 0.2 watt) A/D converters.